US 12,189,534 B2
Cache blocking for dispatches
Saurabh Sharma, Santa Clara, CA (US); Hashem Hashemi, Santa Clara, CA (US); Paavo Pessi, Noormakuu (FI); Mika Tuomi, Noormakuu (FI); Gianpaolo Tommasi, Santa Clara, CA (US); Jeremy Lukacs, Santa Clara, CA (US); and Guennadi Riguer, Markham (CA)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US); and ATI Technologies ULC, Markham (CA)
Filed by ADVANCED MICRO DEVICES, INC., Santa Clara, CA (US); and ATI TECHNOLOGIES ULC, Markham (CA)
Filed on Dec. 29, 2021, as Appl. No. 17/564,474.
Prior Publication US 2023/0205698 A1, Jun. 29, 2023
Int. Cl. G06F 9/46 (2006.01); G06F 9/48 (2006.01); G06F 12/0855 (2016.01)
CPC G06F 12/0855 (2013.01) [G06F 9/4806 (2013.01); G06F 2212/1008 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
executing a first portion of a first dispatch of work items that write data to a cache, the first dispatch comprising a first plurality of portions, wherein an amount of data written to the cache by the first portion of the first dispatch does not exceed a storage capacity of the cache; and
in response to the first portion of the first dispatch of work items completing execution, executing a first portion of a second dispatch of work items that read data written to the cache by the first portion of the first dispatch, the second dispatch comprising a second plurality of portions.