US 12,189,524 B2
Extended memory architecture
Vijay S. Ramesh, Boise, ID (US); Allan Porterfield, Durham, NC (US); and Richard D. Maes, Liberty Lake, WA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Oct. 5, 2022, as Appl. No. 17/960,477.
Application 17/960,477 is a continuation of application No. 16/913,304, filed on Jun. 26, 2020, granted, now 11,481,317.
Prior Publication US 2023/0025291 A1, Jan. 26, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/02 (2006.01); G06F 7/57 (2006.01); G06F 9/38 (2018.01); G06F 11/10 (2006.01); G06F 12/0868 (2016.01); G06F 13/16 (2006.01); G06F 13/42 (2006.01)
CPC G06F 12/0246 (2013.01) [G06F 7/57 (2013.01); G06F 9/3856 (2023.08); G06F 11/1068 (2013.01); G06F 12/0868 (2013.01); G06F 13/1668 (2013.01); G06F 13/4221 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a plurality of computing devices configured according to a reduced instruction set computing (RISC) architecture;
a first communication subsystem coupled to a host and to each of the plurality of computing devices; and
a plurality of second communication subsystems coupled to each of the plurality of computing devices, wherein each of the plurality of second communication subsystems are coupled to at least one hardware accelerator;
wherein each of the plurality of computing devices are configured to:
perform at least a first portion of an extended memory operation within each respective computing device of the plurality of computing devices without transferring data associated with the first portion of the extended memory operation external to the respective computing device; and
receive a result of performing at least a second portion of the extended memory operation from the at least one hardware accelerator.