US 12,189,479 B2
Apparatus and method for detecting and recovering from data fetch errors
Theodros Yigzaw, Sherwood, OR (US); Geeyarpuram N. Santhanakrishnan, Mercer Island, WA (US); Ganapati N. Srinivasa, Portland, OR (US); Jose A. Vargas, Rescue, CA (US); Hisham Shafi, Akko (IL); Michael Mishaeli, Haifa (IL); Ehud Cohen, Kiryat Motskin (IL); Zeev Sperber, Zichron Yaakov (IL); Shlomo Raikin, Sde Eliezer (IL); Mohan J. Kumar, Aloha, OR (US); and Julius Y. Mandelblat, Haifa (IL)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Nov. 23, 2022, as Appl. No. 17/993,591.
Application 17/993,591 is a continuation of application No. 17/356,157, filed on Jun. 23, 2021, abandoned.
Application 17/356,157 is a continuation of application No. 16/292,085, filed on Mar. 4, 2019, granted, now 11,048,587, issued on Jun. 29, 2021.
Application 16/292,085 is a continuation of application No. 13/994,609, granted, now 10,223,204, issued on Mar. 5, 2019, previously published as PCT/US2011/066683, filed on Dec. 22, 2011.
Prior Publication US 2023/0088947 A1, Mar. 23, 2023
Int. Cl. G06F 11/14 (2006.01); G06F 11/10 (2006.01)
CPC G06F 11/1405 (2013.01) [G06F 11/1064 (2013.01)] 25 Claims
OG exemplary drawing
 
1. An apparatus comprising:
error processing hardware logic to detect an error associated with execution of a load operation, the error comprising an uncorrected hardware error;
storage hardware logic to store error log information associated with the error, the error log information comprising at least an address associated with the error, an indication of an instruction that generated the load operation, and an indication of whether the load operation associated with the error is a data load operation or an instruction fetch operation; and
error recovery logic to perform one or more recovery actions based on the error log information.