US 12,189,462 B2
Pausing memory system based on critical event
Noorshaheen Mavungal Noorudheen, Long Beach, CA (US); Sudhakar Ravindra Parab, Bengaluru (IN); and Sanjay Tanaji Shinde, Bangalore (IN)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Sep. 9, 2022, as Appl. No. 17/941,856.
Claims priority of application No. 202241038148 (IN), filed on Jul. 1, 2022.
Prior Publication US 2024/0004745 A1, Jan. 4, 2024
Int. Cl. G06F 11/07 (2006.01); G06F 11/10 (2006.01)
CPC G06F 11/0772 (2013.01) [G06F 11/076 (2013.01); G06F 11/1032 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory sub-system comprising a front-end (FE) device and a set of memory components; and
a processing device, operatively coupled to the FE device and the set of memory components, the memory sub-system comprising one or more components comprising a middle management logic (MML) device and a media controller (MC), the MML device configured to receive commands from the FE device and transmit requests to the MC to perform the received commands, the MML device comprising command identifier logic and the FE device comprising a command queue in which the commands are stored, the FE device configured to perform a plurality of operations comprising:
receiving, from the processing device, critical event trigger data;
storing the critical event trigger data in one or more trigger event logic registers of the FE device;
determining that one or more operations of the memory sub-system correspond to the critical event trigger data; and
in response to determining that the one or more operations of the memory sub-system correspond to the critical event trigger data:
storing a state of the memory sub-system; and
transmitting an interrupt signal to the processing device to initiate debugging operations on the processing device, the interrupt signal comprising the state of the memory sub-system.