| CPC G06F 1/3293 (2013.01) [G06F 1/324 (2013.01); G06F 9/30029 (2013.01); G06F 9/3871 (2013.01)] | 20 Claims |
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1. A hardware system to reduce latency of changing an operating state of a processor from a low-power state to a normal-power state, the hardware system comprising:
memory; and
a processor system coupled to the memory, the processor system configured to:
determine an amount of time that is to be consumed to complete processing of a network packet, which is received via a network, by the hardware system;
select a first time instance at which a notification is to be provided to the processor based at least in part on the amount of time;
prior to a transaction layer packet that is based at least in part on the network packet being provided to the processor by the hardware system, trigger a change of the operating state of the processor from the low-power state to the normal-power state by asynchronously providing the notification to the processor at the first time instance prior to completion of the processing of the network packet by the hardware system, the notification indicating that the transaction layer packet is to be provided to the processor at a second time instance that temporally follows the first time instance, wherein the low-power state is configured to cause the processor to consume a first amount of power, and wherein the normal-power state is configured to cause the processor to consume a second amount of power that is greater than the first amount; and
cause the transaction layer packet to be processed in the normal-power state by providing the transaction layer packet to the processor at the second time instance.
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