US 12,189,451 B2
Low power state staging
Dmitry Vaysman, San Jose, CA (US); Eran Erez, Bothell, WA (US); Judah Gamliel Hahn, Ofra (IL); and Sartaj Ajrawat, Fremont, CA (US)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by Western Digital Technologies, Inc., San Jose, CA (US)
Filed on May 25, 2023, as Appl. No. 18/323,945.
Application 18/323,945 is a continuation of application No. 16/915,910, filed on Jun. 29, 2020, granted, now 11,709,539.
Application 16/915,910 is a continuation in part of application No. PCT/US2018/060752, filed on Nov. 13, 2018.
Claims priority of provisional application 62/930,205, filed on Nov. 4, 2019.
Prior Publication US 2023/0297156 A1, Sep. 21, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 1/32 (2019.01); G06F 1/3225 (2019.01); G06F 1/3234 (2019.01)
CPC G06F 1/3225 (2013.01) [G06F 1/3275 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A data storage device, comprising:
a memory device, wherein the memory device comprises a non-volatile memory device and a volatile memory device; and
a controller coupled to the memory device, wherein the controller is configured to:
receive a request from a host device to enter a non-operational power state;
set a timer to a predetermined period of time;
determine that the timer has expired;
cause the data storage device to enter a transitional state;
cause the data storage device to enter the non-operational power state; and
flush data from the volatile memory device to the non-volatile memory device in response to entering the transitional state.