US 12,189,416 B2
Clock generating circuit and clock distribution network and semiconductor apparatus including the clock generating circuit
Yeon Ho Lee, Icheon-si Gyeonggi-do (KR); and Yong Suk Choi, Icheon-si Gyeonggi-do (KR)
Assigned to SK hynix Inc., Icheon-si Gyeonggi-do (KR)
Filed by SK hynix Inc., Icheon-si Gyeonggi-do (KR)
Filed on Jan. 6, 2023, as Appl. No. 18/094,227.
Claims priority of application No. 10-2022-0115362 (KR), filed on Sep. 14, 2022.
Prior Publication US 2024/0085939 A1, Mar. 14, 2024
Int. Cl. G06F 1/08 (2006.01); G06F 1/10 (2006.01); G06F 1/12 (2006.01)
CPC G06F 1/08 (2013.01) [G06F 1/10 (2013.01); G06F 1/12 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A clock generating circuit comprising:
a buffer circuit configured to non-invert an input clock signal to generate an output clock signal;
a voltage control circuit configured to detect a voltage level change of a power voltage and configured to generate a first control voltage and a second control voltage, the first control voltage and the second control voltage having varying voltage levels according to the detected voltage level change; and
a compensating circuit configured to invert the output clock signal according to the first and second control voltages to generate a feedback signal using a single inversion stage, and configured to provide the feedback signal to the input clock signal,
wherein the feedback signal is a single inversion of the output clock signal.