US 12,189,414 B2
Memory device clock swapping
Kallol Mazumder, Dallas, TX (US); Navya Sri Sreeram, McKinney, TX (US); and Scott E. Smith, Plano, TX (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 29, 2022, as Appl. No. 17/897,957.
Prior Publication US 2024/0069589 A1, Feb. 29, 2024
Int. Cl. G06F 1/08 (2006.01); G06F 1/10 (2006.01)
CPC G06F 1/08 (2013.01) [G06F 1/10 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
clock circuitry configured to generate a first clock signal and a second clock signal based on a system clock signal, the first clock signal and the second clock signal being mutually out of phase;
detection circuitry configured to provide a detection result indicating whether an initial operation of a self-refresh exit operation coincides with a rising edge of the first clock signal or a rising edge of the second clock signal; and
processing circuitry configured to:
receive the first clock signal and the second clock signal and the detection result and, in response, provide an odd clock signal and an even clock signal corresponding to the first clock signal and the second clock signal, respectively; and
provide the odd clock signal and the even clock signal out of phase with the first clock signal and the second clock signal when the detection result coincides with the rising edge of the first clock signal, and to provide the odd clock signal and the even clock signal in phase with the first clock signal and the second clock signal when the detection result coincides with the rising edge of the second clock signal.