| CPC G02F 1/136286 (2013.01) [G02F 1/1368 (2013.01); H01L 27/124 (2013.01); G02F 1/133555 (2013.01); G02F 1/134309 (2013.01)] | 16 Claims |
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1. A display substrate, having a display region, and a peripheral region surrounding the display region; wherein the display substrate comprises:
a base substrate;
a plurality of first conductive structures on the base substrate in the display region and the peripheral region; wherein the plurality of first conductive structures each extend in a first direction and are arranged side by side in a second direction;
an interlayer insulation layer on a side of the first conductive structures away from the base substrate;
a plurality of second conductive structures on a side of the interlayer insulation layer away from the base substrate and in the display region and the peripheral region; wherein the plurality of second conductive structures each extend in the second direction and are arranged side by side in the first direction; and the second conductive structures intersect with the first conductive structures, and are electrically connected with the first conductive structures through vias penetrating through the interlayer insulation layer; and
at least one third conductive structure on the base substrate in at least the display region; wherein
the third conductive structure comprises a plurality of first conductive lines and a plurality of second conductive lines; each first conductive line forms at least a partial structure of one of the first conductive structures, and part of the first conductive structures each comprise two first conductive lines; and each second conductive line forms at least a partial structure of one of the second conductive structures,
the display substrate further comprises:
a plurality of gate lines on the base substrate in the display region and the peripheral region; wherein the plurality of gate lines each extend in the first direction and are arranged side by side in the second direction; and
a plurality of data lines on the base substrate in the display region and the peripheral region; wherein the plurality of gate lines each extend in the second direction and are arranged side by side in the first direction; and
a plurality of sub-pixels on the base substrate in the display region; wherein the sub-pixels are disposed in regions defined by the gate lines and data lines, with the gate lines intersecting with the data lines; the sub-pixels arranged side by side in the first direction form first pixel groups; the sub-pixels arranged side by side in the second direction form second pixel groups; and any adjacent first pixel groups are provided with one of the first conductive structures therebetween,
wherein at least part pairs of adjacent second pixel groups each are provided with one of the second conductive structures between the adjacent second pixel group,
wherein the third conductive structure comprises at least one coil part; the coil part comprises at least two sub-structures extending in different directions; and each of the sub-structures comprises the first conductive line and the second conductive line, and
wherein the coil part comprises three sub-structures, comprising two first sub-structures and one second sub-structure; and the two first sub-structures each extend in the second direction, and are arranged side by side in the first direction, and the second sub-structure is connected between the two first sub-structures,
wherein the display region comprises at least one first region and at least one second region; the third conductive structure is located in the first region; the first region comprises a non-functional region, and a functional region surrounding the non-functional region; the functional region comprises functional sub-regions arranged in a nested manner, and a redundant functional region between adjacent functional sub-regions; each functional sub-region is provided with one coil part;
the display substrate further comprises a redundant coil part on the base substrate; and each redundant functional region is provided with one redundant coil part; and
the redundant coil part comprises a plurality of seventh conductive lines and a plurality of eighth conductive lines in the redundant functional region, with the seventh conductive lines intersecting with the eighth conductive lines; wherein each seventh conductive line is a partial structure of one of the first conductive structures, and each eighth conductive line is a partial structure of one of the second conductive structures, and
wherein a distance between the first conductive line and the seventh conductive line closest thereto in a same one of the first conductive structures ranges from about 2 μm to about 6 μm; and/or
a distance between the eighth conductive line and the second conductive line closest thereto in a same one of the second conductive structures ranges from about 2 μm to about 6 μm,
wherein the redundant coil part comprises two first redundant sub-structures which are arranged side by side in the first direction and each extend in the second direction, and a second redundant sub-structure extending in the first direction and connected between the two first redundant sub-structures; the first redundant sub-structures and the second redundant sub-structure each comprise the seventh conductive line and the eighth conductive line; the eighth conductive line in each first redundant structure extends to a region where the second redundant structure is located, and the seventh conductive line in the second redundant structure extends to a region where each first redundant structure is located;
each seventh conductive line in the first redundant sub-structures comprises a plurality of second conductive sub-lines arranged side by side in the first direction; a gap between adjacent second conductive sub-lines is located between adjacent sub-pixels; and/or
each eighth conductive line in the second redundant sub-structure comprises a plurality of third conductive sub-lines arranged side by side in the second direction; and a gap between adjacent third conductive sub-lines is located between adjacent sub-pixels,
wherein the gap between adjacent second conductive sub-lines has a width ranging from about 2 μm to about 6 μm; and/or
the gap between adjacent third conductive sub-lines has a width ranging from about 2 μm to about 6 μm,
the display substrate further comprises:
a common electrode line on the base substrate in the peripheral region; wherein the common electrode line comprises a first common electrode sub-line extending in the first direction, and a second common electrode sub-line extending in the second direction; the first common electrode sub-line is disposed in a same layer and made of a same material as the first conductive structures; the second common electrode sub-line is disposed in a same layer and made of a same material as the second conductive structures; the first common electrode sub-line is electrically connected to the second common electrode sub-line through a via penetrating through the interlayer insulation layer;
each eighth conductive line of the first redundant sub-structures is electrically connected to the first common electrode sub-line through a via penetrating through the interlayer insulation layer; and/or
each seventh conductive line of the second redundant sub-structure is electrically connected to the second common electrode sub-line through a via penetrating through the interlayer insulation layer.
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