CPC G01S 17/04 (2020.01) [H03M 1/56 (2013.01); H03K 5/2481 (2013.01)] | 14 Claims |
1. A semiconductor device comprising:
a bias generating circuit configured to sample a bias voltage according to a reset signal; and
a current source configured to provide a bias current according to the bias voltage,
wherein the bias generating circuit includes:
a PMOS transistor having a gate and a drain coupled in common; and
a bias sampling capacitor; and
a switch configured to couple a gate of the PMOS transistor and the bias sampling capacitor according to the reset signal.
|