US 12,188,979 B2
Error protection analysis of an integrated circuit
Benjamin Neil Trombley, Hopewell Junction, NY (US); Chung-Lung K. Shum, Wappingers Falls, NY (US); Karl Evan Smock Anderson, Poughkeepsie, NY (US); Bodo Hoppe, Ingersheim (DE); Erica Stuecheli, Austin, TX (US); Shiri Moran, Kiryat Tivon (IL); Patrick James Meaney, Poughkeepsie, NY (US); Arvind Haran, Liberty Hill, TX (US); and Douglas Balazich, Poughkeepsie, NY (US)
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on May 31, 2023, as Appl. No. 18/326,717.
Prior Publication US 2024/0402246 A1, Dec. 5, 2024
Int. Cl. G01R 31/317 (2006.01); G01R 31/3181 (2006.01); G01R 31/3185 (2006.01)
CPC G01R 31/31704 (2013.01) [G01R 31/31705 (2013.01); G01R 31/31816 (2013.01); G01R 31/318525 (2013.01); G01R 31/318583 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for error protection analysis of an integrated circuit, the method comprising:
receiving a design model for the integrated circuit and a list of error checkers associated with the design model;
traversing the design model from each of the error checkers to group storage cells of the design model into checking groups; and
updating the design model to include, for each checking group, a unique group identifier associated with each of the storage cells in the checking group.