US 12,187,607 B2
Method for manufacturing semiconductor substrate, method for manufacturing damascene wiring structure, semiconductor substrate, and damascene wiring structure
Nao Inoue, Hamamatsu (JP); Jo Ito, Hamamatsu (JP); Go Tanaka, Hamamatsu (JP); Atsuya Iima, Hamamatsu (JP); Daiki Suzuki, Hamamatsu (JP); and Katsumi Shibayama, Hamamatsu (JP)
Assigned to HAMAMATSU PHOTONICS K.K., Hamamatsu (JP)
Appl. No. 17/288,642
Filed by HAMAMATSU PHOTONICS K.K., Hamamatsu (JP)
PCT Filed Oct. 30, 2019, PCT No. PCT/JP2019/042668
§ 371(c)(1), (2) Date Apr. 26, 2021,
PCT Pub. No. WO2020/090930, PCT Pub. Date May 7, 2020.
Claims priority of application No. 2018-205351 (JP), filed on Oct. 31, 2018; and application No. 2019-179964 (JP), filed on Sep. 30, 2019.
Prior Publication US 2021/0403320 A1, Dec. 30, 2021
Int. Cl. B81C 1/00 (2006.01); B81B 7/00 (2006.01)
CPC B81C 1/00619 (2013.01) [B81B 7/0006 (2013.01); B81B 2201/042 (2013.01); B81B 2207/07 (2013.01); B81C 2201/0132 (2013.01); B81C 2201/0133 (2013.01); B81C 2201/0142 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor substrate, comprising:
a first step of forming a recess having a bottom surface and a side surface on which scallops are formed by performing a process including isotropic etching on a main surface of a semiconductor substrate;
a second step of performing at least one of a hydrophilic treatment on the side surface of the recess and a degassing treatment on the recess; and
a third step of removing the scallops formed on the side surface of the recess and planarizing the side surface by performing anisotropic wet etching in a state where the bottom surface of the recess is present, wherein
a protective film formed on the side surface is removed between the first step and the second step.