US 12,187,603 B2
Semiconductor package using a polymer substrate
Yung Woo Lee, Gyeonggi-do (KR); Byung Jun Kim, Seoul (KR); Dong Hyun Bang, Seoul (KR); EunNaRa Cho, Seoul (KR); Adrian Arcedera, Chandler, AZ (US); and Jae Ung Lee, Seoul (KR)
Assigned to AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD., Singapore (SG)
Filed by Amkor Technology Singapore Holding Pte. Ltd., Singapore (SG)
Filed on Feb. 6, 2023, as Appl. No. 18/106,203.
Application 18/106,203 is a continuation of application No. 17/086,633, filed on Nov. 2, 2020, granted, now 11,572,269.
Application 17/086,633 is a continuation of application No. 16/255,292, filed on Jan. 23, 2019, granted, now 10,822,226, issued on Nov. 3, 2020.
Application 16/255,292 is a continuation of application No. 15/009,012, filed on Jan. 28, 2016, abandoned.
Claims priority of application No. 10-2015-0014883 (KR), filed on Jan. 30, 2015.
Prior Publication US 2023/0257257 A1, Aug. 17, 2023
Int. Cl. B81B 7/00 (2006.01)
CPC B81B 7/0061 (2013.01) [B81B 2201/0257 (2013.01); B81B 2207/012 (2013.01); H01L 2224/48137 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/15151 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a cavity substrate comprising a substrate top side, a substrate bottom side, a substrate sidewall joining the substrate top side to the substrate bottom side, and a cavity through the substrate top side, wherein the cavity comprises a cavity bottom surface and a cavity sidewall, wherein an inner surface of the cavity sidewall extends from the cavity bottom surface to the substrate top side, and wherein the inner surface of the cavity sidewall and an outer surface of the substrate sidewall define a wall thickness of the substrate sidewall;
an electrical component in the cavity of the cavity substrate;
a planar substrate coupled to the substrate top side, wherein the planar substrate covers the electrical component in the cavity of the cavity substrate;
conductive lands on an external surface of the semiconductor device; and
one or more conductive paths traversing the cavity sidewall and coupling the conductive lands to the electrical component; and
wherein a conductive path of the one or more conductive paths comprises:
a first surface in direct contact with the inner surface of the cavity sidewall; and
a second surface, opposite the first surface, that is exposed.