US 11,856,764 B2
Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells
Jordan D. Greenlee, Boise, ID (US); and John D. Hopkins, Meridian, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Apr. 6, 2021, as Appl. No. 17/223,359.
Prior Publication US 2022/0320129 A1, Oct. 6, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/00 (2006.01); H10B 41/27 (2023.01); H01L 21/768 (2006.01); H10B 43/27 (2023.01)
CPC H10B 41/27 (2023.02) [H01L 21/76802 (2013.01); H01L 21/76889 (2013.01); H10B 43/27 (2023.02)] 21 Claims
OG exemplary drawing
 
1. A method used in forming a memory array comprising strings of memory cells, comprising:
forming a conductor tier comprising conductor material on a substrate;
forming laterally-spaced memory-block regions individually comprising a vertical stack comprising alternating first tiers and second tiers directly above the conductor tier, channel-material strings of memory cells extending through the first tiers and the second tiers;
forming horizontally-elongated lines in the conductor tier between the laterally-spaced memory-block regions, the horizontally-elongated lines being of different composition from an upper portion of the conductor material and comprising metal material; and
after forming the horizontally-elongated lines, forming conductive material in a lower of the first tiers and that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier.