CPC H03M 13/091 (2013.01) [G06F 13/40 (2013.01); H03M 13/611 (2013.01)] | 19 Claims |
1. An electronic circuit comprising:
an interface;
a transmit data register coupled to the interface;
a first storage device coupled to the transmit data register and including a plurality of storage locations, each storage location adapted to store a data unit;
a first serial register coupled between the first storage device and a first output; and
a first cyclic redundancy check (CRC) generation circuit having an input coupled to a first intermediate node that is coupled between an output of the transmit data register and the first storage device, wherein the first CRC generation circuit comprises:
a first CRC generation block configured to provide a first CRC in response to an X-bit data unit and an X-bit polynomial, wherein X is a positive integer greater than 0; and
a second CRC generation block with a collective X-bit input for providing a second CRC in response to an X-bit data unit and a 2X-bit polynomial in a single clock cycle of a clock signal and a 2X-bit data unit and a 2X-bit polynomial in two clock cycles of the clock signal.
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