US 11,855,642 B1
Programmable delay circuit including threshold-voltage programmable field effect transistor
Navneet K. Jain, Milpitas, CA (US); and Venkatesh P. Gopinath, Fremont, CA (US)
Assigned to GlobalFoundries U.S. Inc., Malta, NY (US)
Filed by GlobalFoundries U.S. Inc., Malta, NY (US)
Filed on Sep. 6, 2022, as Appl. No. 17/929,841.
Int. Cl. H03K 5/134 (2014.01); H03K 5/131 (2014.01); H03K 5/00 (2006.01)
CPC H03K 5/134 (2014.07) [H03K 5/131 (2013.01); H03K 2005/00071 (2013.01); H03K 2005/00221 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A structure comprising:
an input node;
an output node;
an inverter connected between the input node and the output node;
a threshold voltage-programmable field effect transistor;
a capacitor electrically connectable to the output node through the threshold voltage-programmable field effect transistor;
a first access device connected between the input node and a gate structure of the threshold voltage-programmable field effect transistor and controlled by a program mode control signal; and
a second access device connected between a power supply and the gate structure of the threshold voltage-programmable field effect transistor and controlled by a delay mode control signal.