US 11,855,626 B1
Asynchronous consensus circuit with stacked linear or paraelectric non-planar capacitors
Amrita Mathuriya, Portland, OR (US); Nabil Imam, Atlanta, GA (US); Ikenna Odinaka, Durham, NC (US); Rafael Rios, Austin, TX (US); Rajeev Kumar Dokania, Beaverton, OR (US); and Sasikanth Manipatruni, Portland, OR (US)
Assigned to KEPLER COMPUTING INC., San Francisco, CA (US)
Filed by Kepler Computing Inc., San Francisco, CA (US)
Filed on Jan. 14, 2022, as Appl. No. 17/648,121.
Application 17/648,121 is a continuation of application No. 17/647,963, filed on Jan. 13, 2022.
This patent is subject to a terminal disclaimer.
Int. Cl. H03K 19/00 (2006.01); H03K 19/23 (2006.01)
CPC H03K 19/0008 (2013.01) [H03K 19/0021 (2013.01); H03K 19/23 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a first input;
a second input; and
a consensus circuitry coupled to the first input and the second input, wherein the consensus circuitry is to generate a consensus output which is indicative of a consensus of the first input and the second input, wherein the consensus circuitry comprises a gate to receive the first input, the second input, and a third input, and wherein and the third input is coupled to an output of the gate which is the consensus output, wherein the gate comprises:
a first capacitor having a first terminal coupled to the first input, and a second terminal coupled to a summing node;
a second capacitor having a third terminal coupled to the second input, and a fourth terminal coupled to the summing node; and
a third capacitor having a fifth terminal coupled to the third input, and a sixth terminal coupled to the summing node, wherein the first capacitor, the second capacitor, and the third capacitor are non-planar stacked capacitors.