US 11,855,223 B2
Self-aligned gate endcap (SAGE) architectures with gate-all-around devices
Biswajeet Guha, Hillsboro, OR (US); William Hsu, Hillsboro, OR (US); Leonard P. Guler, Hillsboro, OR (US); Dax M. Crum, Beaverton, OR (US); and Tahir Ghani, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 13, 2021, as Appl. No. 17/549,827.
Application 17/549,827 is a continuation of application No. 16/017,966, filed on Jun. 25, 2018, granted, now 11,233,152.
Prior Publication US 2022/0102557 A1, Mar. 31, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/78 (2006.01); H01L 21/02 (2006.01); H01L 21/8234 (2006.01); H01L 23/522 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/423 (2006.01)
CPC H01L 29/7856 (2013.01) [H01L 21/02603 (2013.01); H01L 21/823481 (2013.01); H01L 23/5226 (2013.01); H01L 29/0649 (2013.01); H01L 29/0669 (2013.01); H01L 29/0847 (2013.01); H01L 29/42392 (2013.01); H01L 2029/7858 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a first vertical stack of horizontal nanowires above a trench isolation structure;
a second vertical stack of horizontal nanowires laterally spaced apart from the first vertical stack of horizontal nanowires, the second vertical stack of horizontal nanowires above the trench isolation structure; and
a gate endcap isolation structure between the first vertical stack of horizontal nanowires and the second vertical stack of horizontal nanowires, the gate endcap isolation structure over and extending into the trench isolation structure, the gate endcap isolation structure laterally spaced apart and separated from the first vertical stack of horizontal nanowires, and the gate endcap isolation structure laterally spaced apart and separated from the second vertical stack of horizontal nanowires.