US 11,855,180 B2
Gate induced drain leakage reduction in FinFETs
Alexander Reznicek, Troy, NY (US); Takashi Ando, Eastchester, NY (US); Jingyun Zhang, Albany, NY (US); and Ruilong Xie, Niskayuna, NY (US)
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Sep. 20, 2021, as Appl. No. 17/479,250.
Application 17/479,250 is a division of application No. 16/740,958, filed on Jan. 13, 2020, granted, now 11,177,366.
Prior Publication US 2022/0005941 A1, Jan. 6, 2022
Int. Cl. H01L 29/66 (2006.01); H01L 29/08 (2006.01); H01L 29/16 (2006.01); H01L 29/161 (2006.01); H01L 29/78 (2006.01); H01L 29/165 (2006.01); H01L 29/10 (2006.01)
CPC H01L 29/66545 (2013.01) [H01L 29/0847 (2013.01); H01L 29/161 (2013.01); H01L 29/1608 (2013.01); H01L 29/7851 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a fin structure;
a channel epitaxial wrap around layer present on each end of a channel portion of the fin structure, wherein the channel epitaxial wrap around layer is a continuous and conformal layer;
a gate structure including a gate dielectric having end portions in direct contact with the channel epitaxial wrap around layer at said each end of the channel portion, and a middle portion of the gate dielectric is in direct contact with the fin structure at a portion between said each end of the channel portion;
source and drain regions on portions of the fin structure that are on opposing sides of the channel portion; and
spacers separating the gate structure from source and drain regions.