CPC H01L 25/18 (2013.01) [H01L 23/5384 (2013.01); H01L 24/06 (2013.01); H01L 24/14 (2013.01); H01L 24/20 (2013.01)] | 18 Claims |
1. A system in a package, comprising:
a first integrated circuit (IC) chip comprising:
a first data interface comprising a first set of M×N input/output (I/O) pads of a first pad pitch, wherein M and N are positive integers, the first data interface configured to transfer first data in a first data stream; and
an ultra short reach (USR) IC chip coupled to the first IC chip via multiple parallel links, the USR IC chip comprising:
a second data interface comprising a second set of M×N I/O pads, the second set of M×N I/O pads coupled to the first set of M×N I/O pads through the multiple parallel links to communicate the first data stream with the first IC chip;
a third data interface comprising a third set of N I/O pads of a second pad pitch that is greater than the first pad pitch and configured to carry a second data stream of the first data, wherein each of the N I/O pads is configured to operate at a first data rate that is M times higher than a second data rate associated with the second set of M×N I/O pads; and
multiplexer/de-multiplexer circuitry disposed between the second data interface and the third data interface, wherein
the multiplexer/de-multiplexer circuitry is configured to multiplex at least a first portion of the first data stream into a first portion of the second data stream, and to de-multiplex at least a second portion of the second data stream into a second portion of the first data stream.
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