US 11,855,002 B2
Warpage control in microelectronic packages, and related assemblies and methods
Christopher Glancey, Boise, ID (US); and Shams U. Arifeen, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Apr. 26, 2021, as Appl. No. 17/240,734.
Application 17/240,734 is a continuation of application No. 16/549,473, filed on Aug. 23, 2019, granted, now 11,031,353.
Prior Publication US 2021/0257314 A1, Aug. 19, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 23/31 (2006.01)
CPC H01L 23/562 (2013.01) [H01L 23/3121 (2013.01); H01L 23/49861 (2013.01); H01L 2924/3511 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A microelectronic device package, comprising:
a substrate;
one or more microelectronic devices positioned over the substrate;
at least one warpage control layer; and
an encapsulant material positioned between the at least one warpage control layer and the one or more microelectronic devices;
wherein the at least one warpage control layer is coupled to the encapsulant material, the at least one warpage control layer having a first region having a first material having a first coefficient of thermal expansion and a first thickness and a second region having a second material having a second coefficient of thermal expansion different from the first coefficient of thermal expansion and a second thickness greater than the first thickness of the first region.