US 11,854,966 B2
Method of forming semiconductor device including deep vias
Ta-Pen Guo, Hsinchu (TW); Chien-Ying Chen, Hsinchu (TW); Li-Chun Tien, Hsinchu (TW); and Lee-Chung Lu, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jan. 19, 2023, as Appl. No. 18/156,711.
Application 18/156,711 is a continuation of application No. 17/410,782, filed on Aug. 24, 2021, granted, now 11,574,865.
Application 17/410,782 is a continuation of application No. 16/530,808, filed on Aug. 2, 2019, granted, now 11,127,673, issued on Sep. 21, 2021.
Claims priority of provisional application 62/720,051, filed on Aug. 20, 2018.
Prior Publication US 2023/0163066 A1, May 25, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/522 (2006.01); G06F 30/394 (2020.01)
CPC H01L 23/5226 (2013.01) [G06F 30/394 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device, the method comprising:
forming via structures in a first via layer over a transistor layer, the forming the via structures in the first via layer including:
forming a first via structure in the first via layer, the first via structure being included in a first deep via arrangement;
forming conductive segments in a first metallization layer over the first via layer, the forming the conductive segments in the first metallization layer including:
forming M_1st routing segments at least a majority of which, relative to a first direction, have corresponding long axes with lengths which at least equal if not exceed a first permissible minimum value for routing segments in the first metallization layer; and
forming an M_1st interconnection segment having a long axis which is less than the first permissible minimum value, the M_1st interconnection segment being included in the first deep via arrangement.