US 11,854,833 B2
Signal distribution for a quantum computing system
Evan Jeffrey, Santa Barbara, CA (US); and Joshua Yousouf Mutus, Santa Barbara, CA (US)
Assigned to Google LLC, Mountain View, CA (US)
Appl. No. 17/263,619
Filed by Google LLC, Mountain View, CA (US)
PCT Filed Jul. 30, 2018, PCT No. PCT/US2018/044387
§ 371(c)(1), (2) Date Jan. 27, 2021,
PCT Pub. No. WO2020/027779, PCT Pub. Date Feb. 6, 2020.
Prior Publication US 2021/0175095 A1, Jun. 10, 2021
Int. Cl. H01L 21/48 (2006.01); G06N 10/00 (2022.01); H01L 23/498 (2006.01); H01L 33/06 (2010.01)
CPC H01L 21/4857 (2013.01) [G06N 10/00 (2019.01); H01L 23/49822 (2013.01); H01L 33/06 (2013.01)] 37 Claims
OG exemplary drawing
 
1. A method of fabricating a carrier chip for distributing signals among circuit elements of a quantum computing device, the method comprising:
providing a multilayer wiring stack, the multilayer wiring stack comprising alternating layers of dielectric material and wiring;
bonding a capping layer to the multilayer wiring stack, wherein the capping layer comprises a single crystal silicon dielectric layer;
forming a via hole within the capping layer, wherein the via hole extends to a first wiring layer of the multilayer wiring stack;
forming an electrically conductive via within the via hole and electrically coupled to the first wiring layer; and
forming a circuit element on a surface of the capping layer, wherein the circuit element is directly electrically coupled to the electrically conductive via.