US 11,854,822 B2
Anti-oxidation layer to prevent dielectric loss from planarization process
Zhen Yu Guan, Hsinchu (TW); and Hsun-Chung Kuang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jun. 3, 2021, as Appl. No. 17/337,803.
Claims priority of provisional application 63/160,194, filed on Mar. 12, 2021.
Prior Publication US 2022/0293429 A1, Sep. 15, 2022
Int. Cl. H01L 21/3105 (2006.01); H01L 21/02 (2006.01); H01L 21/768 (2006.01)
CPC H01L 21/31053 (2013.01) [H01L 21/0223 (2013.01); H01L 21/02252 (2013.01); H01L 21/76814 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
forming a dielectric layer over a substrate;
patterning the dielectric layer to form an opening in the dielectric layer;
forming a conductive material within the opening of the dielectric layer;
performing a planarization process to remove portions of the conductive material arranged over the dielectric layer thereby forming a conductive feature within the opening of the dielectric layer; and
performing a post-planarization drying process, wherein the post-planarization drying process uses a mixture of a drying solution, a reducing agent, and an inhibitor compound,
wherein the drying solution is configured to remove any cleaning solutions present from prior cleaning processes on the dielectric layer and the conductive feature,
wherein the reducing agent is configured to reduce an oxidation compound comprising the conductive material and oxygen,
wherein the inhibitor compound is configured to bind to a topmost surface of the conductive feature,
wherein an anti-oxidation layer is formed on an upper surface of the conducive feature during the post-planarization drying process.