CPC G11C 7/1072 (2013.01) [G06F 11/073 (2013.01); G06F 11/0778 (2013.01); G06F 11/0787 (2013.01); G06F 11/1044 (2013.01); G06F 11/1048 (2013.01); G06F 11/1068 (2013.01); G11C 7/1006 (2013.01); G06F 11/1008 (2013.01); G11C 5/04 (2013.01); G11C 29/52 (2013.01); G11C 2029/0411 (2013.01)] | 17 Claims |
7. A method of operation of a memory buffer circuit comprising:
receiving, by a memory interface of the memory buffer circuit, at least a portion of a scrambled data word from a first plurality of volatile memory devices in a first memory module;
de-scrambling, by a processing engine of the memory buffer circuit, the portion of the scrambled data word into an unscrambled data word using a pseudo-random process and state information comprising at least one of an address or a bank address; and
transferring, by a host interface of the memory buffer circuit, the unscrambled data word to a host controller in response to a data access request received from the host controller.
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