US 11,854,612 B1
Lifetime mixed level non-volatile memory system
G. R. Mohan Rao, Allen, TX (US)
Assigned to Vervain, LLC, Dallas, TX (US)
Filed by Vervain, LLC, Dallas, TX (US)
Filed on Sep. 26, 2023, as Appl. No. 18/373,071.
Application 14/525,411 is a division of application No. 13/455,267, filed on Apr. 25, 2012, granted, now 8,891,298, issued on Nov. 18, 2014.
Application 18/373,071 is a continuation of application No. 17/203,385, filed on Mar. 16, 2021.
Application 17/203,385 is a continuation of application No. 16/006,299, filed on Jun. 12, 2018, granted, now 10,950,300, issued on Mar. 16, 2021.
Application 16/006,299 is a continuation of application No. 14/950,553, filed on Nov. 24, 2015, granted, now 9,997,240, issued on Jun. 12, 2018.
Application 14/950,553 is a continuation of application No. 14/525,411, filed on Oct. 28, 2014, granted, now 9,196,385, issued on Nov. 24, 2015.
Claims priority of provisional application 61/509,257, filed on Jul. 19, 2011.
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/56 (2006.01); G06F 12/02 (2006.01); G11C 16/34 (2006.01); G06F 11/10 (2006.01); G11C 29/52 (2006.01); G11C 29/00 (2006.01); G11C 16/16 (2006.01)
CPC G11C 11/5635 (2013.01) [G06F 11/1068 (2013.01); G06F 11/1072 (2013.01); G06F 12/0246 (2013.01); G11C 11/5621 (2013.01); G11C 11/5678 (2013.01); G11C 16/16 (2013.01); G11C 16/3495 (2013.01); G11C 29/52 (2013.01); G11C 29/76 (2013.01); G06F 2212/7202 (2013.01); G11C 2211/5641 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A method for storing data comprising:
maintaining an address table for a memory space containing volatile memory and nonvolatile memory space, wherein the nonvolatile memory space includes both multi-level cell (MLC) space and single level cell (SLC) space and the volatile memory includes a random access volatile memory element;
mapping logical and physical addresses adaptable to the system by the address table, wherein the mapping is performed as necessitated by the system to maximize lifetime, and wherein the mapping maps data in at least one of volatile or nonvolatile memories;
controlling during Write access operations and Read access operations a plurality of MLC memory modules, each including at least one MLC nonvolatile memory element and at least one SLC memory module including at least one SLC nonvolatile memory element and associated memory space using at least one controller;
storing received data within a controller memory associated with the at least one controller;
controlling access of the MLC and SLC nonvolatile memory elements and the random access volatile memory element for storage of the received data;
transferring the stored received data from the controller memory to a given one of the MLC nonvolatile memory elements in an associated MLC memory module, operable to store the received data in the given one given one of the MLC nonvolatile memory element as stored data;
retaining the received data in the random access volatile memory as retained data associated with the stored data;
performing a data integrity test on the stored data in the given one of the MLC nonvolatile memory elements in the associated one of the MLC memory modules after at least a Write access operation performed thereon, the performing of the data integrity test further comprising:
reading the stored data to the controller memory;
comparing the stored data in the controller memory in the given one of the MLC nonvolatile memory elements to the retained data that was associated with the stored data in the random access volatile memory by the controller during the Write access operation;
remapping, responsive to a failure of the data integrity test performed on the stored data by the controller, the address space to a different physical range of addresses; and
transferring data corresponding to the retained data to those remapped physical address from those physical addresses determined to have failed the data integrity test.