US 11,854,602 B2
Read clock start and stop for synchronous memories
Aaron John Nygren, Boise, ID (US); Karthik Gopalakrishnan, Cupertino, CA (US); and Tsun Ho Liu, Boston, MA (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Jun. 27, 2022, as Appl. No. 17/850,658.
Claims priority of provisional application 63/287,151, filed on Dec. 8, 2021.
Prior Publication US 2023/0176786 A1, Jun. 8, 2023
Int. Cl. G06F 12/00 (2006.01); G11C 11/4076 (2006.01); G06F 1/08 (2006.01); G06F 1/10 (2006.01); G06F 3/06 (2006.01)
CPC G11C 11/4076 (2013.01) [G06F 1/08 (2013.01); G06F 1/10 (2013.01); G06F 3/0604 (2013.01); G06F 3/0659 (2013.01); G06F 3/0671 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory controller, comprising:
a command queue including a plurality of entries for holding incoming memory access commands;
an arbiter for selecting commands from the command queue for dispatch to a memory; and
a read clock control circuit for monitoring read commands selected for dispatch to the memory, and responsive to a designated condition, commanding the memory to change a state of a read clock from a first state in which the read clock remains active following a postamble period for a read command, to a second state in which the read clock becomes inactive following the postamble period.