| CPC G11C 11/1673 (2013.01) [G11C 11/1675 (2013.01)] | 18 Claims |
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1. A memory system comprising:
a memory array comprising:
a plurality of data columns that are configured to store data and provide a data signal in response to a read operation;
a first plurality of reference columns in the memory array configured to provide same logic 0 reference signals, wherein the first plurality of reference columns are distributed throughout the memory array among the plurality of data columns; and
a second plurality of reference columns in the memory array configured to provide same logic 1 reference signals, wherein the second plurality of reference columns are distributed throughout the memory array among the plurality of data columns;
a column multiplexer configured to:
select a first reference column in the first plurality of reference columns that is closest to a data column in the plurality of data columns from which the data signal is being read; and
select a second reference column in the second plurality of reference columns that is closest to the data column; and
a circuit configured to combine at least the logic 0 reference signal from the first reference column and the logic 1 reference signal from the second referenc column to generate a reference signal for a sense amplifier to identify the data signal provided from the plurality of data columns.
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