US 11,854,490 B1
Displays with gate driver circuitry in an active area
Levent Erdal Aygun, Cupertino, CA (US); Chin-Wei Lin, San Jose, CA (US); Yun Wang, Cupertino, CA (US); Xin Lin, Princeton, NJ (US); Aida R Colon-Berrios, Cupertino, CA (US); Shih Chang Chang, Cupertino, CA (US); Fan Gui, San Jose, CA (US); Mohammad Reza Esmaeili Rad, San Jose, CA (US); Ran Tu, San Jose, CA (US); Warren S Rieutort-Louis, Cupertino, CA (US); Abbas Jamshidi Roudbari, Saratoga, CA (US); Bhadrinarayana Lalgudi Visweswaran, San Mateo, CA (US); Cheng-Chih Hsieh, Santa Clara, CA (US); Ricardo A Peterson, Fremont, CA (US); Shyuan Yang, San Mateo, CA (US); Ting-Kuo Chang, San Jose, CA (US); Tsung-Ting Tsai, San Jose, CA (US); and Yuchi Che, Santa Clara, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Aug. 2, 2022, as Appl. No. 17/879,642.
Claims priority of provisional application 63/355,047, filed on Jun. 23, 2022.
Claims priority of provisional application 63/233,542, filed on Aug. 16, 2021.
Int. Cl. G09G 3/3266 (2016.01); G09G 3/00 (2006.01); H01L 27/12 (2006.01)
CPC G09G 3/3266 (2013.01) [G09G 3/007 (2013.01); H01L 27/124 (2013.01); G09G 2300/0452 (2013.01); G09G 2300/0861 (2013.01); G09G 2310/0286 (2013.01); G09G 2320/0626 (2013.01); G09G 2330/021 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A display with first and second opposing edges, the display comprising:
a plurality of pixels arranged in a light-emitting area, wherein the light-emitting area extends from the first edge to the second edge, wherein each one of the plurality of pixels includes an emissive sub-pixel and a thin-film transistor sub-pixel that controls the emissive sub-pixel, wherein each emissive sub-pixel includes an anode and a cathode, and wherein the emissive sub-pixels have a uniform density across the entire light-emitting area;
a plurality of data lines;
a plurality of gate lines;
display driver circuitry that is configured to provide data to the plurality of pixels using the plurality of data lines;
gate driver circuitry that is configured to provide control signals to the plurality of pixels using the plurality of gate lines, wherein at least a portion of the gate driver circuitry is positioned in the light-emitting area;
a first power supply line in the light-emitting area that provides a first power supply voltage with a first magnitude to a first cathode for a first emissive sub-pixel of a first color;
a second power supply line in the light-emitting area that provides a second power supply voltage with a second magnitude to a second cathode for a second emissive sub-pixel of a second color, wherein the second magnitude is different than the first magnitude; and
a third power supply line in the light-emitting area that provides a third power supply voltage with a third magnitude to a third cathode for a third emissive sub-pixel of a third color, wherein the third magnitude is different than the first and second magnitudes and wherein a difference between a minimum of the first, second, and third magnitudes and a maximum of the first, second, and third magnitudes is greater than 0.5 V.