US 11,854,084 B2
System and method for delaying an executable instruction that would otherwise be executable immediately upon arrival at an executing system
Steven I. Givot, Chicago, IL (US)
Assigned to NYSE Chicago, Inc., Chicago, IL (US)
Filed by NYSE Chicago, Inc., Chicago, IL (US)
Filed on Jun. 13, 2023, as Appl. No. 18/209,296.
Application 18/209,296 is a continuation of application No. 16/593,405, filed on Oct. 4, 2019, granted, now 11,734,761.
Application 16/593,405 is a continuation of application No. 16/152,208, filed on Oct. 4, 2018, granted, now 10,467,698, issued on Nov. 5, 2019.
Application 16/152,208 is a continuation of application No. 15/665,083, filed on Jul. 31, 2017, granted, now 10,127,615, issued on Nov. 13, 2018.
Application 15/665,083 is a continuation in part of application No. 15/181,681, filed on Jun. 14, 2016, abandoned.
Prior Publication US 2023/0325928 A1, Oct. 12, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06Q 40/06 (2012.01); G06Q 40/04 (2012.01); G06F 9/38 (2018.01); G06Q 40/02 (2023.01); G06Q 40/12 (2023.01); G06Q 40/00 (2023.01); G06Q 30/08 (2012.01)
CPC G06Q 40/06 (2013.01) [G06F 9/3856 (2023.08); G06Q 40/04 (2013.01); G06Q 30/08 (2013.01); G06Q 40/00 (2013.01); G06Q 40/02 (2013.01); G06Q 40/12 (2013.12)] 19 Claims
OG exemplary drawing
 
1. A system for intentionally delaying execution of an executable instruction, comprising:
a processor configured to execute programmed instructions stored in non-transitory memory;
an input at which one or more executable instructions are received;
an inbound message queue configured to store a portion of the one or more executable instructions such that each executable instruction of the portion is added to an end of the inbound message queue for processing according to a sequence in which it is received; and
an intentional delay queue specifically configured to store a remaining portion of the one or more executable instructions such that each executable instruction of the remaining portion is inserted into any position within the intentional delay queue for processing according to an order in which it is eligible for processing;
the processor being further configured to:
identify a current executable instruction among the one or more executable instructions stored among the inbound message queue and the intentional delay queue;
determine that a source of the current executable instruction comprises a predefined source from which all executable instructions are to be intentionally delayed,
responsive to determining that the current executable instruction is to be intentionally delayed, delay execution of the current executable instruction for a delay time by moving the current executable instruction to a position in the intentional delay queue for execution after the delay time together with a delay indication, and
execute the current executable instruction after the delay time in accordance with the position in the intentional delay queue.