CPC G06F 9/3881 (2013.01) [G06F 9/3836 (2013.01); G06F 12/084 (2013.01)] | 20 Claims |
1. An inter-core data processing method, configured to be implemented in an electronic device which at least comprises a first core, a second core, a command transmission module and a bus module, wherein the method comprises:
the first core sending a first command to the second core through the command transmission module, wherein the first command indicates that the first core is ready to perform a data processing operation corresponding to a target address, wherein the target address is located in a corresponding memory of the second core;
the second core acquiring a mutex lock of the target address in response to the first command;
the second core returning a second command to the first core through the command transmission module, wherein the second command is configured to inform the first core to start the data processing operation; and
the first core performing the data processing operation corresponding to the target address through the bus module in response to the second command;
wherein before the operation of the first core sending the first command to the second core through the command transmission module, the first core generates a start tag which indicates that the first core is ready to perform the data processing operation; and
wherein after the operation of the first core performing the data processing operation corresponding to the target address through the bus module in response to the second command, the first core generates an end tag which indicates that the first core has completed the data processing operation.
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