US 11,853,669 B2
Relocatable FPGA modules
Michael Riepe, San Jose, CA (US); Kamal Choundhary, Santa Clara, CA (US); Amit Singh, San Jose, CA (US); Shirish Jawale, San Jose, CA (US); Karl Koehler, Fremont, CA (US); Simon Longcroft, London (GB); Scott Senst, Walker, MN (US); Clark Hilbert, San Jose, CA (US); and Kent Orthner, Santa Cruz, CA (US)
Assigned to Achronix Semiconductor Corporation, Santa Clara, CA (US)
Filed by Achronix Semiconductor Corporation, Santa Clara, CA (US)
Filed on Nov. 22, 2021, as Appl. No. 17/532,599.
Prior Publication US 2023/0169251 A1, Jun. 1, 2023
Int. Cl. G06F 30/30 (2020.01); G06F 30/347 (2020.01); G06F 30/392 (2020.01); G06F 30/31 (2020.01); G06F 15/78 (2006.01)
CPC G06F 30/347 (2020.01) [G06F 30/31 (2020.01); G06F 30/392 (2020.01); G06F 15/7825 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
accessing, by one or more processors, a design for a programmable integrated circuit comprising a plurality of clusters disposed on a plurality of cluster rows and a plurality of cluster columns, each cluster comprising programmable logic;
accessing, by the one or more processors, a selection of a selected portion of the design, the selected portion having a width and height;
determining, by the one or more processors, a signature for the selected portion of the design;
determining, by the one or more processors, a signature for each of a plurality of portions of the design, each portion having the width and the height;
based on the signature for the selected portion of the design and the signatures for the plurality of portions of the design, determining, by the one or more processors, a plurality of locations within the plurality of clusters that the selected portion of the design can be relocated to without recompilation; and
causing to be presented, by the one or more processors, a user interface that indicates the selected portion of the design and at least a subset of the determined plurality of locations.