US 11,853,572 B2
Encoding-aware data routing
Raghavendra Gopalakrishnan, Karnataka (IN); and Vivek Kumar, Uttar Pradesh (IN)
Assigned to WESTERN DIGITAL TECHNOLOGIES, INC., San Jose, CA (US)
Filed by Western Digital Technologies, Inc., San Jose, CA (US)
Filed on May 5, 2022, as Appl. No. 17/737,877.
Prior Publication US 2023/0359378 A1, Nov. 9, 2023
Int. Cl. G06F 3/06 (2006.01); G06F 12/02 (2006.01)
CPC G06F 3/064 (2013.01) [G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 12/0253 (2013.01); G06F 3/0604 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A storage device, comprising:
multiple memory devices comprising a first single-level cell (SLC) block, a second SLC block, a multi-level cell (MLC) block; and
a controller coupled to the multiple memory devices, the controller configured to:
compare a first read counter to a second read counter to determine that the first read counter is greater than the second read counter, wherein the first SLC block contains first data and is associated with the first read counter, and wherein the second SLC block contains second data and is associated with the second read counter; and
in response to the determination that the first read counter is greater:
transfer the first data from the first SLC block to a first page of the MLC block, wherein the first page is selected for transfer of the first data based on: (i) the first read counter being greater than the second read counter, and (ii) the first page corresponding to fewer number of senses than a second page of the MLC block; and
transfer the second data from the second SLC block to the second page of the MLC block.