US 11,853,205 B2
Memory device with dynamic cache management
Kishore Kumar Muchherla, Fremont, CA (US); Peter Feeley, Boise, ID (US); Ashutosh Malshe, Fremont, CA (US); Daniel J. Hubbard, Boise, ID (US); Christopher S. Hale, Boise, ID (US); Kevin R. Brandt, Boise, ID (US); Sampath K. Ratnam, Boise, ID (US); Yun Li, Fremont, CA (US); and Marc S. Hamilton, Eagle, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Feb. 21, 2023, as Appl. No. 18/172,205.
Application 18/172,205 is a continuation of application No. 17/374,906, filed on Jul. 13, 2021, granted, now 11,593,261.
Application 17/374,906 is a continuation of application No. 16/697,724, filed on Nov. 27, 2019, granted, now 11,093,385, issued on Aug. 17, 2021.
Application 16/697,724 is a continuation of application No. 15/693,178, filed on Aug. 31, 2017, granted, now 10,509,722, issued on Dec. 17, 2019.
Prior Publication US 2023/0195615 A1, Jun. 22, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/00 (2006.01); G06F 12/02 (2006.01); G06F 12/0891 (2016.01); G06F 3/06 (2006.01); G06F 12/06 (2006.01); G06F 12/00 (2006.01); G11C 11/56 (2006.01)
CPC G06F 12/0253 (2013.01) [G06F 3/064 (2013.01); G06F 3/0629 (2013.01); G06F 3/0634 (2013.01); G06F 3/0688 (2013.01); G06F 3/0689 (2013.01); G06F 12/00 (2013.01); G06F 12/0646 (2013.01); G06F 12/0891 (2013.01); G06F 2212/1044 (2013.01); G06F 2212/2022 (2013.01); G06F 2212/7205 (2013.01); G11C 11/5621 (2013.01); G11C 2211/5641 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a memory array including memory cells; and
a controller coupled to the memory array, the controller configured to:
identify valid data stored in one or more groupings of the memory cells;
designate a storage mode for a target set of memory cells based on the valid data,
wherein the target set of memory cells are configured with a capacity to store up to a maximum number of bits per cell, and
wherein the storage mode is for dynamically configuring the target set of memory cells in as cache memory that stores a number of bits less per cell than the corresponding maximum capacity.