US 11,853,156 B2
Error checking for systolic array computation
Doe Hyun Yoon, Foster City, CA (US); and Norman Paul Jouppi, Palo Alto, CA (US)
Assigned to Google LLC, Mountain View, CA (US)
Filed by Google LLC, Mountain View, CA (US)
Filed on Oct. 7, 2022, as Appl. No. 17/961,623.
Application 17/961,623 is a continuation of application No. 17/410,558, filed on Aug. 24, 2021, granted, now 11,507,452.
Claims priority of provisional application 63/222,549, filed on Jul. 16, 2021.
Prior Publication US 2023/0036421 A1, Feb. 2, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/10 (2006.01); G06F 15/80 (2006.01)
CPC G06F 11/1004 (2013.01) [G06F 15/8046 (2013.01)] 20 Claims
OG exemplary drawing
 
13. A method for data processing by a computation unit, the method comprising:
receiving, by a systolic array of processing elements, first input elements from a first input matrix along a first direction of the systolic array;
receiving, by the processing elements, second input elements from a second input matrix along a second direction of the systolic array;
generating, by a checksum circuit, one or more groups of checksums from the first input elements while the systolic array receives the first input elements;
generating, by the processing elements, an output matrix from the first input matrix, the second input matrix, and the one or more groups of checksums;
receiving, by an output checksum circuit, the output matrix; and
determining, by the output checksum circuit, from the output matrix, an occurrence of one or more errors in the generation of the output matrix.