US 11,852,682 B2
Circuit screening system and circuit screening method
Chi-Che Wu, Hsinchu (TW); Tsung-Yang Hung, Hsinchu County (TW); Jia-Ming Guo, Hsinchu (TW); Yi-Na Fang, Hsinchu (TW); and Ming-Yih Wang, Hsin-Chu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed on Nov. 14, 2022, as Appl. No. 18/055,365.
Application 18/055,365 is a continuation of application No. 17/114,330, filed on Dec. 7, 2020, granted, now 11,500,016.
Prior Publication US 2023/0070575 A1, Mar. 9, 2023
Int. Cl. G01R 31/317 (2006.01)
CPC G01R 31/31725 (2013.01) [G01R 31/31721 (2013.01)] 20 Claims
OG exemplary drawing
 
17. A circuit screening method, comprising:
operating in a first input stage, in which a first testing signal is inputted into a target circuit under test, a supply voltage, whose voltage level locates in an input range, is provided to the target circuit under test, and a clock signal having a first profile is provided to the target circuit under test;
operating in a second input stage after the first input stage, in which a second testing signal different from the first testing signal is inputted into the test target circuit under test, and the supply voltage, whose voltage level relocates in the input range, is provided to the test target circuit under test, and a clock signal having a second profile different from the first profile is provided to the target circuit under test;
wherein the first profile and the second profile has a phase difference.