US 10,512,081 B2
Receiving method and apparatus
Akihiko Nishio, Osaka (JP); Christian Wengerter, Kleinheubach (DE); Hidetoshi Suzuki, Kanagawa (JP); and Masaru Fukuoka, Ishikawa (JP)
Assigned to Panasonic Corporation, Osaka (JP)
Filed by Panasonic Corporation, Osaka (JP)
Filed on Apr. 5, 2018, as Appl. No. 15/946,489.
Application 15/946,489 is a continuation of application No. 15/451,099, filed on Mar. 6, 2017, granted, now 9,967,879.
Application 15/451,099 is a continuation of application No. 14/920,444, filed on Oct. 22, 2015, granted, now 9,629,163, issued on Apr. 18, 2017.
Application 14/920,444 is a continuation of application No. 14/250,101, filed on Apr. 10, 2014, granted, now 9,204,444, issued on Dec. 1, 2015.
Application 14/250,101 is a continuation of application No. 13/919,753, filed on Jun. 17, 2013, granted, now 9,019,925, issued on Apr. 28, 2015.
Application 13/919,753 is a continuation of application No. 13/308,118, filed on Nov. 30, 2011, granted, now 8,509,141, issued on Aug. 13, 2013.
Application 13/308,118 is a continuation of application No. 13/184,382, filed on Jul. 15, 2011, granted, now 8,204,017, issued on Jun. 19, 2012.
Application 13/184,382 is a continuation of application No. 12/846,447, filed on Jul. 29, 2010, granted, now 8,040,832, issued on Oct. 18, 2011.
Application 12/846,447 is a continuation of application No. 12/593,899, granted, now 7,852,807, issued on Dec. 14, 2010, previously published as PCT/JP2008/001569, filed on Jun. 18, 2008.
Claims priority of application No. 2007-161958 (JP), filed on Jun. 19, 2007; application No. 2007-211545 (JP), filed on Aug. 14, 2007; and application No. 2008-056561 (JP), filed on Mar. 6, 2008.
Prior Publication US 2018/0227914 A1, Aug. 9, 2018
This patent is subject to a terminal disclaimer.
Int. Cl. H04W 72/04 (2009.01); H04B 7/12 (2006.01); H04L 1/00 (2006.01); H04L 5/00 (2006.01)
CPC H04W 72/0446 (2013.01) [H04B 7/12 (2013.01); H04L 1/0003 (2013.01); H04L 1/0009 (2013.01); H04L 1/0071 (2013.01); H04L 5/0007 (2013.01); H04L 5/0028 (2013.01); H04L 5/0039 (2013.01); H04L 5/0041 (2013.01); H04L 5/0092 (2013.01); H04W 72/0453 (2013.01); H04L 5/006 (2013.01); H04L 5/0064 (2013.01); H04L 5/0085 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An integrated circuit to control a process, the process comprising:
receiving allocation information indicating one or more Distributed Virtual Resource Blocks (DVRBs) with consecutive DVRB numbers, the DVRBs with the consecutive DVRB numbers that are interleaved being mapped to Physical Resource Blocks (PRBs), a difference between DVRB numbers of two DVRBs that are mapped to PRBs in a same frequency within a subframe being less than or equal to two, and two DVRBs with consecutive DVRB numbers being mapped to two PRBs that are inconsecutive in a frequency domain; and
decoding data based on the allocation information.