CPC H10B 53/30 (2023.02) | 20 Claims |
1. A device comprising:
a first region comprising:
a first conductive interconnect within a first dielectric in a first level;
a second level above the first level, the second level comprising:
an electrode structure on at least a portion of the first conductive interconnect, the electrode structure comprising:
a first conductive hydrogen barrier layer; and
a first conductive material adjacent to the first conductive hydrogen barrier layer;
an insulator layer laterally surrounding the electrode structure; and
a memory device on least a portion of the electrode structure, the memory device comprising a ferroelectric material or a paraelectric material;
a second dielectric spanning the first region, the second dielectric comprising an amorphous, greater than 90% film density hydrogen barrier material, wherein the memory device is directly adjacent to and embedded within the second dielectric;
a third dielectric comprising a first less than 90% film density material on the second dielectric, the third dielectric within a third level above the second level; and
a via electrode structure on at least a portion of the memory device, the via electrode structure comprising:
a second conductive hydrogen barrier layer comprising a lateral portion on the memory device and substantially vertical portions at opposite ends of the lateral portion, wherein the lateral portion and the substantially vertical portions are configured as a cup; and
a second conductive material in contact with the second conductive hydrogen barrier layer,
wherein the via electrode structure further comprises a first portion adjacent to the second dielectric and a second portion adjacent to the third dielectric; and
a second region adjacent to the first region, the second region comprising:
a fourth dielectric comprising dielectric comprising a second less than 90% film density material directly adjacent to the second dielectric and below the third dielectric;
a second conductive interconnect within the first level;
a third conductive interconnect within the third level, wherein the third dielectric extends over the fourth dielectric and wherein the third dielectric laterally surrounds the third conductive interconnect; and
a via structure coupled between the second conductive interconnect and the third conductive interconnect, wherein at least a portion of the via structure is adjacent to the insulator layer.
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