CPC H10B 12/50 (2023.02) [G11C 11/4097 (2013.01); H10B 12/01 (2023.02); G11C 11/408 (2013.01); G11C 11/4091 (2013.01); G11C 11/4093 (2013.01)] | 19 Claims |
1. An apparatus comprising:
a memory cell including:
a first transistor including a charge storage structure and a first channel region separated from the charge storage structure; and
a second transistor including a second channel region coupled to the charge storage structure;
a conductive region coupled to a first portion of the first channel region;
a first data line coupled to a second portion of the first channel region;
a second data line coupled to the second channel region, the second channel region being between the charge storage structure and the second data line, each of the first and second data lines including a length in a first direction;
at least one access line including length in a second direction and separated from the first channel region and the second channel region; and
a trench including a bottom, wherein the charge storage structure is formed in a first location of the trench, the second channel region is formed in a second location of the trench, and the charge storage structure is between the bottom of the trench and the second channel region.
|