US 11,839,070 B1
High density dual encapsulation materials for capacitors and methods of fabrication
Noriyuki Sato, Hillsboro, OR (US); Niloy Mukherjee, San Ramon, CA (US); Mauricio Manfrini, Heverlee (BE); Tanay Gosavi, Portland, OR (US); Rajeev Kumar Dokania, Beaverton, OR (US); Somilkumar J. Rathi, Denver, CO (US); Amrita Mathuriya, Portland, OR (US); and Sasikanth Manipatruni, Portland, OR (US)
Assigned to KEPLER COMPUTING INC., San Francisco, CA (US)
Filed by Kepler Computing Inc., San Francisco, CA (US)
Filed on Dec. 16, 2021, as Appl. No. 17/553,511.
Application 17/553,511 is a continuation of application No. 17/550,904, filed on Dec. 14, 2021.
Int. Cl. H01L 21/00 (2006.01); H10B 53/20 (2023.01); G11C 11/22 (2006.01); H01L 23/31 (2006.01); G11C 5/02 (2006.01); H01L 49/02 (2006.01); H01L 23/538 (2006.01)
CPC H10B 53/20 (2023.02) [G11C 5/025 (2013.01); G11C 11/221 (2013.01); H01L 23/31 (2013.01); H01L 23/5384 (2013.01); H01L 28/75 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a first region comprising:
a first conductive interconnect within a first dielectric in a first level;
a second level above the first level, the second level comprising:
an electrode structure on the first conductive interconnect, the electrode structure comprising:
a first conductive hydrogen barrier layer; and
a first conductive fill material on the first conductive hydrogen barrier layer, wherein the electrode structure comprises a first lateral thickness;
an etch stop layer comprising an insulator, the etch stop layer laterally surrounding the electrode structure;
a memory device comprising a ferroelectric material or a paraelectric material on least a portion of the electrode structure, the memory device further comprising a second lateral thickness, wherein the second lateral thickness is less than the first lateral thickness;
an encapsulation layer comprising a first amorphous, greater than 90% film density hydrogen barrier material directly on a sidewall of the memory device;
a second dielectric spanning the first region, the second dielectric comprising a second amorphous, greater than 90% film density hydrogen barrier material adjacent the encapsulation layer;
a via electrode on at least a portion of the memory device, the via electrode comprising:
a second conductive hydrogen barrier layer comprising a lateral portion in contact with the memory device;
substantially vertical portions directly adjacent to the second dielectric; and
a second conductive fill material adjacent to the second conductive hydrogen barrier layer;
a second region adjacent to the first region, the second region comprising:
a second conductive interconnect within the first level, wherein
the second level further comprising:
a third conductive interconnect;
a via structure coupled between the second conductive interconnect and the third conductive interconnect; and
a third dielectric on the etch stop layer, the third dielectric directly adjacent to the second dielectric and the encapsulation layer, wherein the third dielectric comprises a less than 90% film density material, and wherein the third dielectric laterally surrounds a portion of the via structure.