	US 11,838,525 B2
	Image compression circuitry and image compression method
Micael Lacson Magpayo, Tokyo (JP); Hirobumi Furihata, Tokyo (JP); and Takashi Nose, Tokyo (JP)
Assigned to Synaptics Incorporated, San Jose, CA (US)
Filed by Synaptics Incorporated, San Jose, CA (US)
Filed on Jun. 28, 2022, as Appl. No. 17/852,340.
Application 17/852,340 is a continuation of application No. 16/589,950, filed on Oct. 1, 2019, granted, now 11,418,801.
Claims priority of application No. 2018-190483 (JP), filed on Oct. 5, 2018.
Prior Publication US 2022/0329838 A1, Oct. 13, 2022
Int. Cl. H04N 19/42 (2014.01); H04N 19/176 (2014.01); H04N 19/423 (2014.01); H04N 19/70 (2014.01)

CPC H04N 19/439 (2014.11) [H04N 19/176 (2014.11); H04N 19/423 (2014.11); H04N 19/70 (2014.11)]

26 Claims

1. Image compression circuitry, comprising:

first-stage compression circuitry configured to:

sequentially receive a plurality of input blocks each comprising pixel data for a plurality of pixels;

generate a plurality of first-stage compressed blocks by compressing the plurality of input blocks through a plurality of first-stage compression methods; and

generate a plurality of first-stage decompressed blocks by decompressing the plurality of first-stage compressed blocks;

first-stage selector circuitry configured to:

select first-stage-selected decompressed blocks from among the plurality of first-stage decompressed blocks; and

select first-stage-selected compressed blocks corresponding to the first-stage- selected decompressed blocks from among the plurality of first-stage compressed blocks;

second-stage compression circuitry configured to:

generate a plurality of second-stage compressed blocks by compressing the plurality of input blocks through a plurality of second-stage compression methods, wherein the plurality of second-stage compression methods is different than the plurality of first-stage compression methods; and

generate a plurality of second-stage decompressed blocks by decompressing the plurality of second-stage compressed blocks,

wherein the second-stage compression circuitry is different than the first-stage compression circuitry; and

second-stage selector circuitry configured to:

select second-stage-selected compressed blocks from among the first-stage- selected compressed blocks and the plurality of second-stage compressed blocks; and

output the second-stage-selected compressed blocks.