	US 11,838,403 B2
	Method and apparatus for an ultra low power VLSI implementation of the 128-bit AES algorithm using a novel approach to the shiftrow transformation
Alekhya Muthineni, San Antonio, TX (US); and Eugene John, San Antonio, TX (US)
Assigned to BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEM, Austin, TX (US)
Filed by The Board of Regents of the University of Texas System, Austin, TX (US)
Filed on Apr. 10, 2020, as Appl. No. 16/845,556.
Claims priority of provisional application 62/833,258, filed on Apr. 12, 2019.
Prior Publication US 2020/0328877 A1, Oct. 15, 2020
Int. Cl. H04L 9/06 (2006.01); G06F 1/26 (2006.01)

CPC H04L 9/0631 (2013.01) [G06F 1/26 (2013.01)]

10 Claims

1. An encryption and decryption apparatus comprising:

memory storing a plaintext, an encryption key, a current state matrix, a resultant state matrix, and a ciphertext;

a processor;

a first, a second, a third, and a fourth plurality of interconnections; and

a first, a second, a third, a fourth, and a fifth four-by-one multiplexers; and

circuitry configured to perform clock gating;

the processor, the memory, the circuitry, the first, second, third, fourth, and fifth four-by-one multiplexers, and the first, second, third, and fourth plurality of interconnections to perform an iterated Rijndael block cipher to convert the plaintext to the ciphertext using the encryption key by applying a SubBytes operation, a ShiftRows operation, a MixCols operation, and an AddRoundKey operation,

wherein the SubBytes operation is performed in the same step as the ShiftRows operation by including a look-up table,

wherein the plaintext is transformed into the current state matrix and the resultant state matrix as intermediate values during intermediate operations of the block cipher, and

wherein the ShiftRows operation comprises:

using the first plurality of interconnections to connect a first row of the current state matrix to the first four-by-one multiplexer in an order of elements of the first row, wherein an arrangement of the first plurality of interconnections preserves the order of elements of the first row of the current state matrix as an order of inputs into the first four-by-one multiplexer;

transmitting from the first four-by-one multiplexer to the fifth four-by-one multiplexer the elements of the first row of the resultant state matrix, in the order received by the first four-by-one multiplexer;

using the second plurality of interconnections to connect a second row of the current state matrix to the second four-by-one multiplexer, wherein an arrangement of the second plurality of interconnections shifts an order of elements of the second row of the current state matrix by one to the left for input into the second four-by-one multiplexer;

transmitting from the second four-by-one multiplexer to the fifth four-by-one multiplexer the elements of the second row of the resultant state matrix, in the order received by the second four-by-one multiplexer;

using the third plurality of interconnections to connect a third row of the current state matrix to the third four-by-one multiplexer, wherein an arrangement of the third plurality of interconnections shifts an order of elements of the third row of the current state matrix by two to the left for input into the third four-by-one multiplexer;

transmitting from the third four-by-one multiplexer to the fifth four-by-one multiplexer the elements of the third row of the resultant state matrix, in the order received by the third four-by-one multiplexer;

using the fourth plurality of interconnections to connect a fourth row of the current state matrix to the fourth four-by-one multiplexer, wherein an arrangement of the fourth plurality of interconnections shifts an order of elements of the fourth row of the current state matrix by three to the left for input into the fourth four-by-one multiplexer;

transmitting from the fourth four-by-one multiplexer to the fifth four-by-one multiplexer the elements of the fourth row of the resultant state matrix, in the order received by the fourth four-by-one multiplexer; and

transmitting from the fifth four-by-one multiplexer to the resultant state matrix each element in a row-by-row fashion, in an order the elements were received by the fifth four-by-one multiplexer.