US 11,837,623 B2
Integrated circuit having vertical routing to bond pads
Eric Miller, Lompoc, CA (US); Christian M. Boemler, Lompoc, CA (US); Justin Gordon Adams Wehner, Goleta, CA (US); Drew Fairbanks, Santa Barbara, CA (US); and Sean P. Kilcoyne, Lompoc, CA (US)
Assigned to Raytheon Company, Waltham, MA (US)
Filed by Raytheon Company, Waltham, MA (US)
Filed on Oct. 12, 2020, as Appl. No. 17/068,223.
Prior Publication US 2022/0115423 A1, Apr. 14, 2022
Int. Cl. H01L 27/146 (2006.01); H01L 27/148 (2006.01); H01L 23/498 (2006.01); H01L 21/311 (2006.01); H01L 23/488 (2006.01); H01L 23/48 (2006.01); H01L 23/485 (2006.01); H04N 25/75 (2023.01)
CPC H01L 27/1469 (2013.01) [H01L 21/311 (2013.01); H01L 23/481 (2013.01); H01L 23/485 (2013.01); H01L 23/488 (2013.01); H01L 23/49827 (2013.01); H01L 27/148 (2013.01); H01L 27/1462 (2013.01); H01L 27/14632 (2013.01); H01L 27/14634 (2013.01); H01L 27/14636 (2013.01); H01L 27/14685 (2013.01); H04N 25/75 (2023.01)] 8 Claims
OG exemplary drawing
 
1. An assembly including first and second wafers directly bonded to each other, comprising:
direct bonding posts electrically connecting the first and second wafers;
an oxide layer on direct bonding sides of the first and second wafers; and
a direct bonding interface at bonding surfaces of the first and second wafers, wherein the assembly includes a backside surface and a frontside surface, the first wafer includes IO signal connections vertically routed to the direct bonding interface by a first one of the bonding posts on the first wafer bonded to a first one of the bonding posts on the second wafer, and the second wafer comprises vertical routing of the IO signal connections from first one of the bonding posts on the second wafer to IO pads on a backside surface of the assembly.