US 11,837,529 B2
Semiconductor package with top circuit and an IC with a gap over the IC
Barry Jon Male, West Granby, CT (US); Paul Merle Emerson, Madison, AL (US); and Sandeep Shylaja Krishnan, Kerala (IN)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Mar. 18, 2022, as Appl. No. 17/698,855.
Application 17/698,855 is a division of application No. 16/202,925, filed on Nov. 28, 2018, granted, now 11,302,611.
Prior Publication US 2022/0208657 A1, Jun. 30, 2022
Int. Cl. H01L 23/495 (2006.01); H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01)
CPC H01L 23/49513 (2013.01) [H01L 21/563 (2013.01); H01L 21/565 (2013.01); H01L 23/3114 (2013.01); H01L 23/4952 (2013.01); H01L 23/49548 (2013.01); H01L 24/09 (2013.01); H01L 24/17 (2013.01); H01L 24/32 (2013.01); H01L 24/49 (2013.01); H01L 24/73 (2013.01); H01L 2924/1304 (2013.01); H01L 2924/141 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A semiconductor device assembly method, comprising:
mounting a first circuit on a die pad of a leadframe, the first circuit having a region;
mounting a second circuit on the first circuit via interconnects, in which the region is spaced from the second circuit by a gap and by the interconnects;
forming an attachment layer between the first and second circuits and around the interconnects, in which the attachment layer and the first and second circuits enclose at least a part of the gap over the region; and
encapsulating the first and second circuits, the attachment layer, and the at least part of the gap by a mold compound.