US 11,837,518 B2
Coated semiconductor dies
Michael Todd Wyant, Dallas, TX (US); Matthew John Sherbin, Dallas, TX (US); Christopher Daniel Manack, Flower Mound, TX (US); Patrick Francis Thompson, Allen, TX (US); and You Chye How, Melaka (MY)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Aug. 26, 2020, as Appl. No. 17/003,382.
Prior Publication US 2022/0068744 A1, Mar. 3, 2022
Int. Cl. H01L 23/31 (2006.01); H01L 23/552 (2006.01); H01L 21/56 (2006.01); H01L 21/78 (2006.01); H01L 21/683 (2006.01)
CPC H01L 23/3185 (2013.01) [H01L 21/561 (2013.01); H01L 21/568 (2013.01); H01L 21/78 (2013.01); H01L 23/3171 (2013.01); H01L 23/552 (2013.01); H01L 21/6836 (2013.01); H01L 2221/68336 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A chip scale package (CSP), comprising:
a semiconductor die;
a conductive terminal coupled to the semiconductor die; and
a non-conductive coat including a top portion covering a backside of the semiconductor die and a sidewall portion covering a sidewall of the semiconductor die, the non-conductive coat having a thickness of less than 45 microns, the sidewall portion of the non-conductive coat having a uniform thickness on the sidewall of the semiconductor die and the top portion having a width corresponding to a sum of a width of the semiconductor die and twice of the uniform thickness of the sidewall portion, wherein a strip of the sidewall of the semiconductor die is exposed and the sidewall portion terminates at the strip of the sidewall, wherein the strip of the sidewall abuts a frontside of the semiconductor die opposite the backside.