US 11,837,507 B2
Gate structure and method of forming same
Shahaji B. More, Hsinchu (TW); Chandrashekhar Prakash Savant, Hsinchu (TW); and Chun Hsiung Tsai, Xinpu Township (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 11, 2022, as Appl. No. 17/811,651.
Application 17/811,651 is a division of application No. 16/564,243, filed on Sep. 9, 2019, granted, now 11,404,327.
Prior Publication US 2022/0344210 A1, Oct. 27, 2022
Int. Cl. H01L 21/8238 (2006.01); H01L 21/28 (2006.01); H01L 21/3213 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 27/092 (2006.01); H01L 29/49 (2006.01)
CPC H01L 21/82385 (2013.01) [H01L 21/28088 (2013.01); H01L 21/32134 (2013.01); H01L 21/823821 (2013.01); H01L 27/0924 (2013.01); H01L 29/4966 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a gate stack over an active region of a substrate, the gate stack comprising:
a conductive material;
a first protective layer lining sidewalls and a bottom surface of the conductive material;
a second protective layer lining sidewalls and a bottom surface of the first protective layer, the first protective layer and the second protective layer comprising different materials;
an N-type work function layer lining sidewalls and a bottom surface of the second protective layer, an upper portion of the N-type work function layer being in physical contact with an upper portion of the first protective layer;
a gate dielectric layer lining sidewalls and a bottom surface of the N-type work function layer;
a P-type work function layer between the N-type work function layer and the gate dielectric layer; and
a third protective layer between the N-type work function layer and the P-type work function layer, the upper portion of the N-type work function layer being in physical contact with an upper portion of the P-type work function layer.