US 11,837,461 B2
Semiconductor device and manufacturing method thereof
Shunpei Yamazaki, Tokyo (JP); Jun Koyama, Kanagawa (JP); Hiroyuki Miyake, Kanagawa (JP); Kei Takahashi, Kanagawa (JP); Kouhei Toyotaka, Kanagawa (JP); Masashi Tsubuku, Kanagawa (JP); Kosei Noda, Kanagawa (JP); and Hideaki Kuwabara, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on Sep. 2, 2020, as Appl. No. 17/010,151.
Application 15/372,493 is a division of application No. 13/799,246, filed on Mar. 13, 2013, granted, now 9,666,678, issued on May 30, 2017.
Application 17/010,151 is a continuation of application No. 16/121,700, filed on Sep. 5, 2018, granted, now 10,777,682.
Application 16/121,700 is a continuation of application No. 15/372,493, filed on Dec. 8, 2016, granted, now 10,074,747, issued on Sep. 11, 2018.
Application 13/799,246 is a continuation of application No. 12/904,565, filed on Oct. 14, 2010, granted, now 8,421,068, issued on Apr. 16, 2013.
Claims priority of application No. 2009-238885 (JP), filed on Oct. 16, 2009.
Prior Publication US 2021/0143281 A1, May 13, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/786 (2006.01); H01L 27/12 (2006.01); H01L 29/26 (2006.01); G06K 19/077 (2006.01); H01L 21/8236 (2006.01); H01L 23/66 (2006.01); H01L 27/088 (2006.01); H01L 29/24 (2006.01); H01L 29/66 (2006.01); G11C 7/00 (2006.01); G11C 19/28 (2006.01); H02M 3/07 (2006.01)
CPC H01L 29/78609 (2013.01) [G06K 19/07758 (2013.01); H01L 21/8236 (2013.01); H01L 23/66 (2013.01); H01L 27/0883 (2013.01); H01L 27/1225 (2013.01); H01L 29/24 (2013.01); H01L 29/26 (2013.01); H01L 29/66969 (2013.01); H01L 29/7869 (2013.01); H01L 29/78696 (2013.01); G11C 7/00 (2013.01); G11C 19/28 (2013.01); H01L 2223/6677 (2013.01); H02M 3/07 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first transistor over a glass substrate, the first transistor comprising a first oxide semiconductor layer where a channel formation region is provided,
a second transistor over the glass substrate, the second transistor comprising a second oxide semiconductor layer where a channel formation region is provided,
wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises indium and zinc,
wherein a conductive layer is provided between the substrate and the first oxide semiconductor layer,
wherein a first insulating layer is provided between the conductive layer and the first oxide semiconductor layer,
wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer are over and in direct contact with the first insulating layer,
wherein a channel length of the first transistor is longer than a channel length of the second transistor,
wherein no conductive layer is provided between the substrate and the second oxide semiconductor layer, and
wherein a size of crystal grains in each of the first oxide semiconductor layer and the second oxide semiconductor layer is greater than or equal to 1 nm and smaller than or equal to 20 nm.