US 11,837,456 B2
Continuous gate and fin spacer for advanced integrated circuit structure fabrication
Heidi M. Meyer, Hillsboro, OR (US); Ahmet Tura, Portland, OR (US); Byron Ho, Hillsboro, OR (US); Subhash Joshi, Hillsboro, OR (US); Michael L. Hattendorf, Portland, OR (US); and Christopher P. Auth, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Aug. 18, 2022, as Appl. No. 17/890,969.
Application 17/890,969 is a division of application No. 15/859,323, filed on Dec. 29, 2017, granted, now 11,462,436.
Claims priority of provisional application 62/593,149, filed on Nov. 30, 2017.
Prior Publication US 2022/0406650 A1, Dec. 22, 2022
Int. Cl. H01L 21/762 (2006.01); H01L 49/02 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 21/311 (2006.01); H01L 29/08 (2006.01); H01L 27/11 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/308 (2006.01); H01L 27/092 (2006.01); H01L 29/51 (2006.01); H01L 21/285 (2006.01); H01L 21/28 (2006.01); H01L 21/033 (2006.01); H01L 21/768 (2006.01); H01L 23/532 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 27/088 (2006.01); H10B 10/00 (2023.01)
CPC H01L 21/76224 (2013.01) [H01L 21/0337 (2013.01); H01L 21/28247 (2013.01); H01L 21/28568 (2013.01); H01L 21/3086 (2013.01); H01L 21/31105 (2013.01); H01L 21/31144 (2013.01); H01L 21/76816 (2013.01); H01L 21/823431 (2013.01); H01L 21/823481 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 21/823842 (2013.01); H01L 21/823857 (2013.01); H01L 21/823871 (2013.01); H01L 21/823878 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 23/53238 (2013.01); H01L 23/53266 (2013.01); H01L 27/0886 (2013.01); H01L 27/0924 (2013.01); H01L 28/24 (2013.01); H01L 29/0847 (2013.01); H01L 29/516 (2013.01); H01L 29/6653 (2013.01); H01L 29/66795 (2013.01); H01L 29/66818 (2013.01); H01L 29/785 (2013.01); H01L 29/7843 (2013.01); H01L 29/7846 (2013.01); H01L 29/7848 (2013.01); H01L 29/7854 (2013.01); H10B 10/12 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method of fabricating an integrated circuit structure, the method comprising:
forming a fin comprising silicon, the fin having a lower fin portion and an upper fin portion;
forming an insulating structure directly adjacent sidewalls of the lower fin portion of the fin;
forming first and second gate structures over the upper fin portion and over first and second portions of the insulating structure, respectively;
forming a dielectric material conformal with the upper fin portion of the fin, conformal with the first and second gate structures, and conformal with a third portion of the insulating structure between the first gate structure and the second gate structure;
forming a hardmask material over the dielectric material;
recessing the hardmask material to expose a portion of the dielectric material conformal with the upper fin portion of the fin and conformal with the first and second gate structures, the recessed hardmask material covering a portion of the dielectric material conformal with the third portion of the insulating structure between the first gate structure and the second gate structure; and
anisotropically etching the dielectric material and subsequently removing the recessed hardmask material to form a first dielectric spacer along a sidewall of the first gate structure and a second dielectric spacer along a sidewall of the second gate structure, the second dielectric spacer continuous with the first dielectric spacer over the third portion of the insulating structure between the first gate structure and the second gate structure.