CPC G11C 7/1072 (2013.01) [G06F 1/10 (2013.01); G06F 1/12 (2013.01); G11C 7/1006 (2013.01); G11C 7/222 (2013.01)] | 20 Claims |
1. A system, comprising:
a host device operable to:
generate a first frame clock; and
transmit one or more frames of data based at least in part on the first frame clock;
a memory device comprising a plurality of memory cells and operable to:
receive the one or more frames of data;
the memory device further comprising a multiplexing circuit operable to:
align a second frame clock generated at the memory device with the first frame clock; and
the host device further comprising a delay component operable to:
receive a return clock signal from the memory device.
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