US 11,837,318 B2
Clock locking for packet based communications of memory devices
James Brian Johnson, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jun. 17, 2022, as Appl. No. 17/843,244.
Application 17/843,244 is a continuation of application No. 16/951,705, filed on Nov. 18, 2020, granted, now 11,373,691.
Claims priority of provisional application 62/951,811, filed on Dec. 20, 2019.
Prior Publication US 2022/0374039 A1, Nov. 24, 2022
Int. Cl. G11C 7/10 (2006.01); G06F 1/10 (2006.01); G06F 1/12 (2006.01); G11C 7/22 (2006.01)
CPC G11C 7/1072 (2013.01) [G06F 1/10 (2013.01); G06F 1/12 (2013.01); G11C 7/1006 (2013.01); G11C 7/222 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system, comprising:
a host device operable to:
generate a first frame clock; and
transmit one or more frames of data based at least in part on the first frame clock;
a memory device comprising a plurality of memory cells and operable to:
receive the one or more frames of data;
the memory device further comprising a multiplexing circuit operable to:
align a second frame clock generated at the memory device with the first frame clock; and
the host device further comprising a delay component operable to:
receive a return clock signal from the memory device.