US 11,837,316 B1
Apparatuses and methods to mask write operations
Scott E. Smith, Plano, TX (US); and Harish V. Gadamsetty, Allen, TX (US)
Assigned to MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Jul. 12, 2022, as Appl. No. 17/812,139.
Int. Cl. G11C 7/08 (2006.01); G11C 7/10 (2006.01)
CPC G11C 7/08 (2013.01) [G11C 7/1009 (2013.01); G11C 7/1039 (2013.01); G11C 7/1096 (2013.01)] 21 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a memory array comprising a first sense amplifier stripe, a second sense amplifier stripe, and a mat of memory cells formed between the first and second sense amplifier stripe, wherein sense amplifiers of the first sense amplifier stripe are coupled to a first set of local input/output (I/O) lines and sense amplifiers of the second sense amplifier stripe are coupled to a second set of local I/O lines;
an input/output (I/O) circuit configured to receive write data via a plurality of data terminals and corresponding mask data via a data mask terminal, wherein the mask data indicates which bits of the write data are to be masked from being written to the memory array, wherein storage of the write data at the memory array mat is based on a map to the plurality of data terminals; and
a column decoder configured to receive the data mask signal, wherein, during a write operation, the column decoder is configured to independently set each of a plurality of write enable signals based on individual bits of the mask data and based on the map of the plurality of data terminals to the memory array mat, wherein a first subset of the plurality of write enable signals are each configured to control provision of a respective portion of the write data to the first plurality of local I/O lines and a second subset of the plurality of write enable signals are configured to control provision of a respective portion of the write data to the second plurality of local I/O lines.